Validation of European high capacity rad-hard FPGA.. (VEGAS)
Validation of European high capacity rad-hard FPGA and software tools
Start date: Jan 1, 2016,
End date: Dec 31, 2018
VEGAS proposes to address the key challenge of European non-dependence and competitivness regarding rad-hard FPGA for space applications. VEGAS will evaluate (following ESCC rules) and validate the first rad-hard FPGA in 65nm to directly compete with the US offering and reach TRL 7. The VEGAS project sets clear and measurable main objectives to reach a TRL 7 from TRL 5 (end of BRAVE project) as follows:1. Validation by end users of rad-hard FPGA developped under the BRAVE project – TRL 6 achieved2. Space evaluation of the first rad-hard FPGA developped under the BRAVE project – TRL 7 achieved3. Software CAD tools improvement by including timing and SEE mitigation toolsVEGAS will complement the ongoing ESA funded BRAVE project. BRAVE covers all hardware and software development to reach a first prototype of NG-FPGA-MEDIUM (30k LUTs) and NG-FPGA-LARGE (130k LUTs) . VEGAS will cover all required steps to ESCC evaluate / validate the BRAVE NG-FPGA-MEDIUM and NG-FPGA-LARGE prototype and add additional software tools to reach a competitive software offering.
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