The development of formal methods for the verification of computer systems is recognizedas a grand challenge by many research institutions. A successful approach for the verification ofsystems consists in modelling the system to be verified by a mathematical structure andin expressing behavioral properties in a logical formalism. The assumption that programs arefinite-state is usually too restrictive and model-checking techniques for infinite-state systemshave flourished these last 20 years. Our research program is motivated by the following assessment: most of model-checking techniques to verify infinite-state systems are mainly interested on the control and less on the data values stored by local or global program variables.In this project, the applicant shall develop verification techniques for systems heavily manipulating data, will design relevant formal specification languages to express properties on data, develop algorithms using SMT solvers that are essential for computer-aided verification. This latter method is mastered by the members of the host institution, Analysis of Computer Systems Group at New York University CS Department.In view of expanding the applicant's skills and competencies, the research training objectives aremainly to get a new expertise in an emerging technology mixing verification and automated deduction, to reach a position of professional maturity by initiating a new research team in the return host dedicated to SMT techniques and to provide transfer of knowledge by the supervision of early-stage researchers and by proposing new curriculum in master programmes.