Shrink-Path of Ultra-Low Power Superconducting Ele.. (S-PULSE)
Shrink-Path of Ultra-Low Power Superconducting Electronics
Start date: Jan 1, 2008,
End date: Jun 30, 2010
The project supported joint efforts of European academic and industrial groups in the superconductive technologies field
The Support Action S-PULSE aims to prepare Superconducting Electronics (SE) for the technology generation beyond the CMOS scaling limits ("beyond CMOS"). Scaling laws in CMOS technology indicate that some concepts cannot be simply extrapolated, and new physical effects that have been negligible up to now, have to be taken into account in the future. Due to the total different physical base in SE, it never had a scaling law, and quantum limits define the ultimate speed. This provides already demonstrated logic operation speed above 100 GHz with typically power dissipation of 1 aJ per logic operation with a 1 µm feature size metal based process. The European activities in SE are currently coordinated by the non-profit Society FLUXONICS e.V., a SCENET initiative under FP6 for a dynamic technology platform in SE. As a major outcome of this network, a circuit foundry for SE was established, a cell library was made available and a first roadmap was drawn up in the field. S-PULSE supports joint efforts of European academic and industrial groups in the superconducting technologies field. The action is to strengthen the vital link between research and development on the one hand and the industrial view on the other hand, bring together industrial expectations and visionary extrapolation and current status of technology, intensify the exchange of knowledge and ideas, take charge of education, and win public interest. The overall strategy of S-PULSE is to broaden the FLUXONICS network and to promote the formation of a European Technology Platform (ETP) to develop and implement a Strategic Research Agenda in the field of ultra-low power superconducting electronics down to the nano-scale domain. With the view on the formation of an industrial guided ETP in the field of SE, the SA is expected to strengthen the competitiveness of the European nanoelectronics industry and to make SE technologies ready to compete with other technologies in the world markets.
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