Materials Synergy Integration for a Better Europe (BET-EU)
Materials Synergy Integration for a Better Europe
Start date: 01 Jan 2016,
End date: 31 Dec 2018
The proposal integrates synergies in the area of Advanced Functional Materials & Nanotechnologies for a better Europe, targeting the specific field of paper electronics, aiming to bridge gaps and capacity building in science and technology identified in Uninova & I3N cluster by twinning with outstanding EU institutions with unique capabilities to progress on fundamental understanding of nanocellulose & device properties at the micro/nanoscale; to manufacture paper electronics, predict materials and devices behavior and their integration. These will master the Portuguese cluster to an international leadership position in this increasingly complex multidisciplinary science and technology field. Moreover, this will allow them to define a Strategic Research Agenda and a Science & Technology Roadmap for the future, with strong regional impact. The objectives of this proposal are tuned with the TWINN-2015 call “The specific challenge is to address networking gaps and deficiencies between the research institutions of the low performing Member States and regions and internationally leading counterparts at EU level”This is done by: University of Cambridge, one of the top Universities in the world, internationally-recognized leader in design and modeling of thin film electronic circuits and applications; Fraunhofer Institute for Ceramic Technologies and Systems, Dresden, Germany, among the world leaders in characterization of nanomaterials and device properties; VTT, Finland, among the world leaders in Printed Electronics, which will co-operate via: a comprehensive program of cross-fertilisation of scientists and technologists, education and hands-on training programs for new research staff, consolidation of acquired know-how, full integration and growth of supply chain in the emerging paper electronics field from advances in nanocellulose materials technology to innovation in device architectures up to their manufacturing.
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