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MAsk less lithoGraphy for IC manufacturing (MAGIC) (MAGIC)
Start date: Jan 1, 2008, End date: Dec 31, 2010 PROJECT  FINISHED 

Description MAGIC has supported the development of e-beam based maskless lithography technology in Europe: Two parallel lithography tool developments for 32nm CMOS and beyond and on lithography infrastructure.In the CMOS manufacturing environment, the mask-based optical lithography technique is up to now driving solution to deal with all industry concerns. Nevertheless, this solution becomes less effective for each new technology node. Effectively, it requires more and more complex and expensive masks due to the introduction of optical proximity correction and phase shift techniques. The blow up of the tool prices play also an important role in the overall cost of ownership of this technique. This trend opens opportunity for the Mask-Less Lithography (ML2) technology, based on multi-beam principles and developped by the two European companies MAPPER and IMS Nanofabrication AG. The cost effective model of the ML2 option in association with the high resolution capability of the electron beam lithography and a reasonable throughput target represents an attractive alternative for lithography and is supported by some key CMOS manufacturers around the world, like TSMC, STMicroelectronics, QIMONDA, TOSHIBA, and Texas Instruments.This project proposes to support the development of ML2 technology in Europe. It is composed of two linked poles. The first one will be focused on MAPPER and IMMS-NANO tools developments with the objective to deliver a first ML2 alpha platform compatible with 32 nm half pitch technology before 2010, aligned with the semiconductor manufacturer requirements. In relation with this activity, the program will develop the required infrastructure for the usage of this tools in an industrial environment. Among the tasks to be addressed, there is a delivery of a reliable software platform to treat the data base preparation and to provide solutions for ML2 related electron proximity effects. The last concern of this project will be to demonstrate the ability to integrate CMOS processes in real manufacturing conditions on the ML2 platform developpeed by the tool partners.
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