Fast Anneal of Compound semiconductors for Integra.. (FACIT)
Fast Anneal of Compound semiconductors for Integration of new Technologies
Start date: Jan 1, 2015,
End date: Dec 31, 2016
"The CMOS industry relies on the capabilities of engineers to control atomic positions at sub-nm scale across several interfaces. The formation of abrupt interfaces is heavily dependent on the thermal budget during their formation and of any other subsequent thermal treatments during device fabrication. As device dimensions decrease, the thicknesses of all junctions and interfaces must be reduced so that they do not become the major fractional volume of the whole device. In that framework, ultra fast annealing is becoming a key technology to enable the fabrication of nano scaled devices.In parallel to this evolution, CMOS technology has seen a materials revolution in recent years. The introduction of high-k dielectrics at 45 nm and of FINFET technology at 22nm extended the lifespan of devices reliant on Si channels. Replacing silicon with high-mobility channels such as Ge and InGaAs will be the next major materials revolution. Whatever the method used to co integrate SiGe and InGaAs, such materials are both very different from Si, in particular with respect to thermal treatments. Co-processing of SiGe pFET and InGaAs nFET is therefore extremely challenging. Device processing on InGaAs nFET should not exceed the allowed thermal budget that SiGe can withstand or vice-versa. Ultra fast annealing will therefore be a key technology to enable the co-integration of Ge and InGaAs.We propose in this project to explore fast (ms) anneal of high-m channels as a generic vehicle to reduce the thermal budget of critical modules. We will in particular focus on InGaAs, as it is the less mature technology with respect to SiGe-based devices. The three main challenges for a successful integration of InGaAs-based MOSFETs in future VLSI technology are clearly identified: (i) fabrication of nanoscale InGaAs “patches”, the active channels, on silicon (ii) high capacitance, low interface state density gate dielectric and (iii) low contact and access resistance in the source/drain regions."
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