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Compound Semiconductors for 3D integration (COMPOSE3)
Start date: Nov 1, 2013, End date: Oct 31, 2016 PROJECT  FINISHED 

COMPOSE3 aims to develop 3D stacked circuits in the front end of line of Complementary Metal Oxide Semiconductor (CMOS) technology, based on high mobility channel materials. The final objective is a 3D stacked SRAM cell, designed with gates length taken from the 14nm technology node. This technology will provide a new paradigm shift in density scaling combined with a dramatic increase in the power efficiency of CMOS circuits. Our synergistic approach is based on the use of high mobility channel materials such as SiGe and InGaAs, utilized in fully depleted metal-oxide-semiconductor field effect transistor (MOSFET), for p and n channel MOSFETs respectively. The low processing temperatures (<600ºC) that can be used for high mobility channels are indeed advantageous for an intimate 3D stacking. COMPOSE3 also exploits the knowledge accumulated in Europe for the layer transfer of ultra-thin semiconductors. Wafer bonding and layer transfer is a critical process module that will be used to enable 3D stacking of high mobility channels. The overall objectives of COMPOSE3 will address the substrate, device and circuit issues. One objective will be to validate InGaAs layer transfer for implementation on 300mm wafers. Another objective will be to benchmark InGaAs nFETs with relevant contact dimensions against planar and non-planar Si based solutions at the 14nm node and beyond. The final objective will be to integrate, on 300mm wafers, monolithic 3D CMOS circuits with 14nm node gates based on n-type InGaAs devices on top of p-type (Si)Ge devices which are independently optimized. COMPOSE3 is extremely well aligned with the strategic agenda of the leading European IC manufacturer, and also exploits its innovation for the benefit of a European SME. It gathers the main European leaders in the advanced nanoelectronics R&D arena.
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