Agile RF Transceivers and Front-Ends for Future Sm.. (ARTEMOS)
Agile RF Transceivers and Front-Ends for Future Smart Multi-Standard Communications Applications
Start date: Apr 1, 2011,
End date: Mar 1, 2014
This project aims at developing architecture and technologies for implementing agile radio frequency (RF) transceiver capacities in future radio communication products. These new architecture and technologies will be able to manage multi-standard (multi-band, multi-data-rate, and multi-waveform) operation with high modularity, low-power consumption, high reliability, high integration, low costs, low PCB area, and low bill of material (BOM).This will not just require smart RF architectures in advanced CMOS and BiCMOS technology, but also need incorporating of e.g. MEMS technologies and novel simulation methodology for achieving these complex optimizations.Multi-standard multi-band terminals integrating all standards (e.g. GSM/EDGE, UMTS, LTE,) and beyond that additional wireless communications systems for mobile devices (such as Wi-Fi, GPS, WirelessHD, WirelessUSB, NFC, PMR, all digital TV standards, etc.) in a single radio architecture with the lowest number of external SAW or BAW filters and power amplifiers. Frequency agile high dynamic range digital friendly RF architectures suitable for nanoscale (Bi)CMOS together with tuneable filters are the key innovations proposed for this project.Today, the analog RF frontend simply duplicates the circuitry for each band. Due to the severe signal constraints in a cell phone and limitations of the current technologies and architectures, it is not possible to create an integrated solution.A tunable RF frontend radio is required which can cover all bands and bandwidths in a range from 0.3GHz to 5GHz, meeting all specifications within a mobile device. This requires homogeneous or heterogeneous integration of a set of complete new tunable architectures and technologies (high-Q on-chip inductors, tunable MEMS capacitors, MEMS switches and resonators or tunable BAW/SAW filters and integrated passive devices processes) with existing (Bi)CMOS technologies.
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