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Dual-channel CMOS for (sub)-22 nm high performance logic (DUALLOGIC)
Start date: Dec 1, 2007, End date: May 31, 2011,
We propose to develop for the first time a dual-channel CMOS technology comprising high channel mobility (high-µ) Ge pMOS and III-V compound semiconductor nMOS transistors co-integrated on the same complex engineered substrate on Si. This offers a high performance booster as an option for the 22 nm technology creating competitive advantage for the European nanoelectronics industry. In addition, hi ...
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