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Towards a Gaussian Network-on-Chip (GNOC)
Start date: 01 Aug 2008, End date: 31 Jul 2012 PROJECT  FINISHED 

As chip multi-processor architectures are replacing single-processor architectures and reshaping the semiconductor industry, chip designers can hardly use their old models and benchmarks anymore. While designers were used to deterministic and reliable performance in the chips, they now face networks with unreliable traffic patterns, unreliable throughput and unreliable delays, hence making it hard to provide any guaranteed Quality-of-Service (QoS). In this proposal, we argue that chip designers should focus on the possible set of traffic patterns in their Network-on-Chip (NoC) architectures. We first show how to provide deterministic QoS guarantees by exploiting these patterns. Then, we explain why the cost of providing deterministic guarantees might become prohibitive, and defend an alternative statistical approach that can significantly lower the area and power. To do so, we introduce Gaussian-based NoC models, and show how they can be used to evaluate link loads, delays and throughputs, as well as redesign the routing and capacity allocation algorithms. Finally, we argue that these models could effectively complement current benchmarks, and should be a central component in the toolbox of the future NoC designer.
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