4 European Projects Found
Searched on 125080 European Projects
FINISHED
Semiconductor Equipment Assessment for Key Enabling Technologies (SEA4KET)
Start date: Nov 1, 2013, End date: Oct 31, 2016,
SEA4KET (Semiconductor Equipment Assessment for Key Enabling Technologies) is an IP proposal taking the consequent step from equipment R&D to equipment assessment experiments. The strategic objective is to effectively combine resources and expertise in a joint assessment of novel equipment for key enabling technologies to foster and accelerate the successful transfer of novel European equipment in ...
Read Project
26
Partners Participants
FINISHED
Thermoplastically deformable circuits for embedded randomly shaped electronics (TERASEL)
Start date: Oct 1, 2013, End date: Sep 30, 2016,
The overall aim of the TERASEL project is the development, the industrial implementation and the application in a wide range of domains of large area, cost-effective, randomly shaped electronics and sensor circuit technologies. More specifically the TERASEL objectives are the following : To develop a basic technology platform for rigid large-area randomly shaped electronic circuits. Key common fe ...
Read Project
16
Partners Participants
FINISHED
Silicon Quantum Wire Transistors (SQWIRE)
Start date: Sep 1, 2010, End date: Aug 31, 2013,
Description
SQWIRE develops industry compatible CMOS technology based on novel Si nanowire transistor structures.The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. As has been demonstrated both theoretically and experimentally, nanowire MOS t ...
Read Project
10
Partners Participants
FINISHED
Dual-channel CMOS for (sub)-22 nm high performance logic (DUALLOGIC)
Start date: Dec 1, 2007, End date: May 31, 2011,
We propose to develop for the first time a dual-channel CMOS technology comprising high channel mobility (high-µ) Ge pMOS and III-V compound semiconductor nMOS transistors co-integrated on the same complex engineered substrate on Si. This offers a high performance booster as an option for the 22 nm technology creating competitive advantage for the European nanoelectronics industry. In addition, hi ...
Read Project
